Moderate field hole and electron injection from one interface of MIM or MIS structures

ABSTRACT

A graded oxide MIM or MIS structure employs band gap grading of the insulator oxide so that holes or electrons (depending on voltage bias) can be injected into the insulator oxide under moderate electric field conditions from the contact at one interface. Electron or hole injection from the opposite interface is blocked due to the larger insulator band gap near this interface. A graded oxide metal-silicon dioxide-silicon (MGOS) semiconductor structure may be fabricated by forming several pyrolytic or CVD SiO 2  layers over a relatively thick thermal SiO 2  layer, with the pyrolytic SiO 2  layers having sequentially increasing excess Si content. This structure may also be fabricated by controlled Si ion implantation in the thermal SiO 2  layer.

BACKGROUND OF THE INVENTION

The present invention generally relates to semiconductor devices whichuse a graded band gap structure to promote the injection of holes orelectrons at one interface of an insulator under moderate electric fieldconditions while, simultaneously, electron or hole injection from theopposite interface is blocked. More particularly, the present invention,in a preferred embodiment, relates to a graded oxide metal-silicondioxide-silicon (MGOS) semiconductor structure which is useful inperforming a memory function.

Semiconductor memory devices in various configurations are known in theart. One such device, known as a beam addressable MOS, employs ametal-oxide-semiconductor structure, including a PN junction, whereincharges are stored in the structure by writing with an electron beam.Readout is also performed with an electron beam, but at a lower currentlevel. The readout is not totally destructive in that upwards of 10readouts can be performed before the charge in a memory cell must berenewed. The advantage of this device is that very high memory densitiescan be achieved. Among the disadvantages, however, are the requirementfor an electron beam with a high vacuum, precision electron optics anddeflection circuitry which result in a high cost.

FET memory devices are also known in the art. One such device employs aMI₁ I₂ S structure wherein I₁ and I₂ denote first and second insulatorlayers. The I₁ I₂ interface may include a metallic impurity whichprovides a well-defined electron trapping region. The presence orabsence of trapped electrons in this region is used to define a memoryfunction either by different values of capacitance of the structure orby monitoring the value of source-drain current as affected by thetrapped electron charges in the presence of suitable-applied gatevoltages. Metallic impurities are not always required at the I₁ I₂interface as the same effect can be realized by using two differentkinds of insulators. For example, one such known device employs a MNOSstructure where a thin oxide film is first formed on a siliconsubstrate, and over this thin oxide film is laid a much thicker siliconnitride film. In this structure, electrons or holes are trapped in thesilicon nitride layer. This particular structure has the advantage, whencompared with the beam addressable MOS structure, of requiring muchsimpler equipment for performing the reading and writing operations inthe memory device. There is a disadvantage associated with thisparticular structure, however, and that relates to the thin oxide layer.This oxide layer must be quite thin, on the order of about 20Å thick, inorder to allow tunneling of the electrons or holes from the Sisubstrate. Reliability problems have been encountered with memorydevices with this thin tunnel oxide layer because of the high fieldsacross it during operation.

SUMMARY OF THE INVENTION

The present invention uses a graded band gap structure to make a chargestorage device wherein injection of holes or electrons from one contactis possible without compensating injection of electrons or holes fromthe other contact. An example of a structure employing this band gapreduction is an MGOS FET to perform a memory function. Morespecifically, the MGOS structure employs hole trapping near the Si--SiO₂interface of the gate structure in a FET configuration. The "write" stepinvolves hole injection from the gate electrode under moderate voltagebias and transport to the Si--SiO₂ interface where some of thepositively-charged holes are trapped in a very stable manner. The"erase" step involves electron injection from the gate electrode undermoderate negative voltage bias and transport to the Si--SiO₂ interfacewhere the electrons would annihilate trapped holes very readily. The"read" operations uses the transconductance of the silicon surface tosense the charged state of the oxide region near the Si--SiO₂ interfaceand uses low grade voltages to prevent further charging of this region.

The band gap graded structure may be fabricated by forming severalpyrolytic or CVD SiO₂ layers over a relatively thick thermal SiO₂ layerwith the pyrolytic SiO₂ layers having sequentially increasing excess Sicontent. The structure may also be fabricated by controlled Si ionimplantation in the thermal SiO₂ layer.

BRIEF DESCRIPTION OF THE DRAWINGS

Other advantages, aspects and uses of the invention will become apparentfrom the following detailed description, taken in connection with theaccompanying drawings, in which:

FIG. 1 is an energy band diagram of a conventional MOS structure;

FIG. 2 is an energy band diagram similar to that of FIG. 1, except thatthe band gap of the oxide continuously decreases toward the metalelectrode interface;

FIG. 3 is an energy band diagram which is a stepped approximation thecontinuously graded energy band gap represented by FIG. 2;

FIG. 4 is a cross-sectional view of an MGOS structure which exhibits thecharacteristics of the energy band diagram shown in FIG. 3;

FIG. 5 is the energy band diagram of the MGOS structure of FIG. 4 forpositive gate bias indicating hole injection and capture;

FIG. 6 is an energy band diagram of the MGOS structure of FIG. 4 fornegative gate bias indicating electron injection and annihilation of atrapped hole; and

FIG. 7 is a generalized cross-sectional view of a MGOS FET structureaccording to the invention.

DESCRIPTION OF THE PREFERRED EMBODIMENT

In the energy band diagram of a conventional MOS structure shown in FIG.1, the ε_(v) level is the valence level and the ε_(c) level is theconduction level in the silicon substrate. The conduction level ε_(c) istypically one electron volt higher than the valence level ε_(v). Theε_(f) level is the fermi level of the metal electrode, in this case,aluminum. The fermi level ε_(f) in the energy diagram lies somewherebetween the valence level ε_(v) and the conduction level ε_(c) of thesilicon substrate. Between the silicon substrate and the aluminumcontact is an insulator of thermal SiO₂. In this insulator, the energylevel difference between the valence level and the conduction level ison the order of nine electron volts. In addition, the difference betweenthe fermi level ε_(f) of the aluminum contact and the conduction levelin the thermal SiO₂ is on the order of three electron volts. As aresult, the thermal SiO₂ represents a substantial barrier to conductionbetween the silicon substrate and the aluminum contact.

By reducing the band gap of the insulator layer of SiO₂ near theAl--SiO₂ interface, holes or electrons (depending on voltage bias) canbe injected into the insulator under moderate electric field conditionsfrom the aluminum contact at this interface. Simultaneously, electron orhole injection from the opposite Si--SiO₂ interface is blocked due tothe larger insulator band gap near this interface. This graded band gapstructure is represented by the energy band diagram of FIG. 2. Thecontinuous grading of the insulator band gap, as illustrated by FIG. 2,could be achieved by ion implantation of silicon, for example, atcontrolled depths adjacent to the Al--SiO₂ interface.

According to a preferred embodiment of the invention, the continuousgrading of the band gap of the insulator, as shown in FIG. 2, is astepped approximation, as illustrated in FIG. 3. The specific structurewhich produces the energy band gap diagram, shown in FIG. 3, is shown ina generalized cross-sectional view in FIG. 4. Starting with a singlecrystal silicon substrate, a relatively thick thermal SiO₂ insulatorlayer is grown. Over this thermal oxide insulator layer are depositedsuccessive pyrolytic or chemical vapor deposition (CVD) SiO₂ layers. InFIG. 4, three such layers are shown, but any number of layers may beused. Each pyrolytic oxide layer is relatively thin compared to theoverall thermal oxide insulator layer; and each successive pyrolyticoxide layer has an increasing amount of excess silicon. It is known thatpyrolytic oxide layers can be formed with excess silicon as described,for example, in U.S. Pat. No. 3,649,884. The number of pyrolytic layers,the thickness of each layer, and the amount of excess silicon in eachsuccessive layer is a matter of design choice. It will be understood bythose skilled in the art, however, that a closer approximation to thecontinuously graded band gap, as represented by FIG. 2, may be achievedby many small steps. The thermal oxide layer, on the other hand, must besufficiently thick when compared with the graded oxide layers to preventany charge trapping or detrapping in the graded oxide layers from beingsensed by the silicon substrate. This thick thermal oxide layer avoidsthe reliability problems encountered with memory devices with thintunnel oxide layers like the MNOS structure.

FIG. 5 is an energy band diagram for a positive gate bias applied to themetal contact in the structure shown in FIG. 4. In other words, for apositive gate bias, the fermi level ε_(f) of the aluminum contact issubstantially lowered with respect to the valence level ε_(v) of thesilicon substrate. Under this condition for gate bias, holes representedby open circles tunnel from the gate electrode into the first pyrolyticoxide layer valence band, and then tunnel sequentially from one oxidelayer to the next, as represented by the solid arrows. The hole iscaptured with about 50Å of the Si--SiO₂ interface, as represented by thedashed arrows. An accumulation of holes at this interface provides acharge storage which can be used to perform a memory function. That is,the "write" step involves hole injection from the gate under moderatepositive voltage bias and tunneling to the Si--SiO₂ interface where someof the positively-charged holes are trapped in a very stable manner.

With the application of a negative gate bias, the fermi level ε_(f) ofthe aluminum contact is raised substantially above the conduction levelε_(c) of the silicon substrate, as shown in FIG. 6. Under this conditionof negative bias, electrons are injected at the aluminum contact intothe first pyrolytic oxide layer conduction band, and then tunnelsequentially from one oxide layer to the next. Once in the conductionband of the thermal oxide layer, the electrons may recombine withpreviously-trapped holes. Thus, this mechanism provides an "erase" stepwhich involves electron injection from the gate under moderate negativevoltage bias and tunneling to the Si--SiO₂ interface where the electronsannihilate trapped holes very readily.

The "read" operation uses the transconductance of the silicon surface tosense the charge state of the oxide region near the Si--SiO₂ interfaceat low gate voltages to prevent further charging of this region. Becauseof the thickness of the thermal oxide layer, charge trapping ordetrapping in the graded pyrolytic oxide layers is not sensed by thesilicon during the "read" operations. Also the magnitude of the appliedfield during the "read" operation is substantially smaller than thefield applied for injection.

A MGOS FET device is shown in FIG. 7. The device employs a gatestructure like that shown in FIG. 4 but is otherwise conventional. Anarray of these FET devices would provide for long-term storage,non-destructive readout and low voltage drive requirements.

While the invention has been described in terms of a preferredembodiment, those skilled in the art will understand that variousmodifications can be made in the practice of the invention withoutdeparting from the scope of the appended claims. For example, althoughthe preferred embodiment of the invention has been described in terms ofa MOS or MIS structure, the teachings of the invention are equallyapplicable to MIM or metal-insulator-metal structures. Moreover, whilethe gate structure of the preferred embodiment has been described ascomprising an aluminum contact, those skilled in the art will recognizethat other metals or semiconductors could be used. Specifically,polycrystalline silicon could be deposited over the pyrolytic oxidelayers to form the gate electrode contact.

We claim:
 1. A metal-insulator-metal or metal-insulator-semiconductorstructure .[.wherein the band gap of the insulator layer near oneinterface only is reduced.]..Iadd.comprising an insulator having aregion of reduced band gap disposed near one insulator-metal interfaceonly .Iaddend.to provide an injection region where holes or electrons,depending on voltage bias, can be injected into .[.the.]. .Iadd.said.Iaddend.insulator under moderate electric field conditions from thecontact at .[.this.]. .Iadd.said one insulator-metal .Iaddend.interfacewhile, simultaneously, electron or hole injection from the oppositeinterface is blocked due to the large insulator band gap near .[.this.]..Iadd.said opposite .Iaddend.interface. .[.2. The structure of claim 1comprising a silicon substrate having thereon a relatively thick thermaloxide insulator layer and a metal or semiconductor electrical contact onthe thermal oxide insulator layer, said thermal oxide having adecreasing band gap in the vicinity of the electrical contact interface,said decreasing band gap being produced by ion implantation..]. .[.3.The structure recited in claim 1 comprising a silicon substrate having afirst relatively thick thermal oxide insulator thereon over which isdeposited a plurality of relatively thin pyrolytic oxide layers, eachsuccessively deposited pyrolytic oxide layer containing an increasingexcess silicon content, and a metal or semiconductor contact on the lastdeposited pyrolytic oxide layer..].
 4. A graded oxidemetal-.Iadd.gate.Iaddend.-silicondioxide.Iadd.gate-silicon.Iaddend.-silicon 14 substrate .[.MGOS.]. FETstructure having an injection region adjacent to .[.the.]. .Iadd.saidmetal .Iaddend.gate .[.electrode.]., said injection region comprising a.[.thin.]. .Iadd.region which exhibits a .Iaddend.graded band gap. 5.The .[.MGOS.]. FET structure as recited in claim 4 wherein .[.the.]..Iadd.said .Iaddend.gate .[.structure.]. .Iadd.insulator.Iaddend.comprises a .[.relatively thick.]. thermal oxide formed on.[.a.]. .Iadd.said .Iaddend.silicon substrate and .Iadd.said injectionregion comprises .Iaddend.a plurality of .[.relatively thin.]. pyrolyticoxide layers formed over .[.the.]. .Iadd.said .Iaddend.thermal oxide,each successive pyrolytic oxide layer containing an increasing.[.excess.]. silicon content .Iadd.relative to the amount of silicon inthe as grown thermal oxide.Iaddend..
 6. In a MOS FET device forperforming a memory function said device being of the type comprising asilicon substrate having source and drain regions formed therein and aninsulated gate structure formed between said source and drainregions.[., the improvement wherein the band gap of the insulator of theinsulated gate structure is reduced near the gate electrical contactinterface.]. .Iadd.comprising a region of reduced band gap forming aportion of said insulated gate structure disposed near the interfacebetween the insulator and the gate electrode of said insulated gatestructure .Iaddend.to provide an injection region wherein holes orelectrons, depending on voltage bias, can be injected into .[.the.]..Iadd.said .Iaddend.insulator under moderate electric field conditionsfrom .[.the.]. .Iadd.said .Iaddend.gate .[.electrical contact.]..Iadd.electrode .Iaddend.while, simultaneously, electron or holeinjection from the .[.substrate.]. interface .Iadd.between saidsubstrate and said insulator .Iaddend.is blocked due to the largeinsulator band gap at .[.this.]. .Iadd.said last mentioned.Iaddend.interface.
 7. The MOS FET device of claim 6 wherein .[.theinsulator.]. .Iadd.said region of reduced band gap .Iaddend.comprises a.[.thermal oxide.]. .Iadd.region .Iaddend.having a decreasing band gapin the vicinity of the .[.gate electrical contact.]. interface.[., saiddecreasing band gap being produced by ion implantation.]. .Iadd.betweensaid gate electrode and said insulator.Iaddend..
 8. The MOS FET deviceof claim 6 wherein .[.the.]. .Iadd.said .Iaddend.insulator .[.comprisesa first relatively thick.]. .Iadd.is a .Iaddend.thermal oxide .[.layerover which is deposited.]. .Iadd.and said region of reduced band gap is.Iaddend.a plurality of .[.relatively thin.]. pyrolytic oxide layers,each successively deposited pyrolytic oxide layer containing .[.anincreasing silicon content.]. .Iadd.more silicon than the previouslydeposited layer and each of said layers containing more silicon than theas grown thermal oxide.Iaddend.. .Iadd.9. Ametal-insulator-semiconductor structure comprising a silicon substratehaving a thermal oxide insulator thereon over which is deposited atleast one relatively thin oxide layer, each successively deposited oxidelayer containing more silicon than the previously deposited oxide layerand each of said layers containing more silicon than the as grownthermal oxide insulator, and a metal or semiconductor contact on thelast deposited oxide layer. .Iaddend. .Iadd.10. A graded oxide metalgate-silicon dioxide-silicon FET structure comprising a siliconsubstrate, a gate oxide of silicon dioxide disposed thereon and aninjection region adjacent to said metal gate, said injection regioncomprising at least one relatively thin oxide layer formed over saidgate oxide layer, each successive thin oxide layer containing moresilicon than the previously formed oxide layer and each of said layerscontaining more silicon than said gate oxide. .Iaddend. .Iadd.
 1. In aMOS FET device for performing a memory function said device being of thetype comprising a silicon substrate of one conductivity type, a pair ofspaced apart regions of opposite conductivity type in said substrate andan insulated gate structure disposed between said pair of regions, theimprovement wherein the insulator of said insulated gate structurecomprises a first layer of silicon oxide over which is deposited atleast one relatively thin oxide layer, each successively deposited oxidelayer containing more silicon than the previously formed oxide layer andeach of said layers containing more silicon than said first layer ofsilicon oxide. .Iaddend. .Iadd.12. The structure of claim 1 wherein saidsemiconductor is a silicon substrate, said insulator is a thermal oxideand said region of reduced band gap is a region of said insulator whichexhibits a continuously decreasing band gap due to a continuouslyincreasing content of silicon over that contained in the as grownthermal oxide as said region approaches said one insulator-metalinterface and, a metal or semiconductor electrical contact disposed onsaid insulator. .Iaddend. .Iadd.13. The structure recited in claim 1wherein said semiconductor is a silicon substrate, said insulator is athermal oxide and said region of reduced band gap is a plurality ofdeposited pyrolytic oxide layers each successively deposited layercontaining more silicon than the previously deposited layer and each ofsaid layers containing more silicon than the as grown thermal oxide, anda metal or semiconductor contact deposited on the last deposited of saidpyrolytic oxide layers. .Iaddend. .Iadd.14. Ametal-insulator-semiconductor structure comprising a silicon substrate,a silicon oxide insulator disposed on said substrate and at leastanother silicon oxide layer disposed on said insulator having a siliconcontent therein in excess of that in said silicon oxide insulator, and aconductive contact on said at least another oxide layer. .Iaddend..Iadd.15. A metal-insulator-semiconductor structure comprising asubstrate of semiconductor material, a first layer of an oxide of saidsemiconductor material disposed on said substrate, at least anotherlayer of an oxide of said semiconductor material having a semiconductormaterial content therein in excess of that in said first layer disposedon said first layer to reduce the band gap of said at least anotherlayer, and a conductive contact on said at least another layer..Iaddend. .Iadd.16. A metal-insulator-semiconductor structure accordingto claim 15 wherein said semiconductor material is silicon, said firstlayer of an oxide is silicon dioxide and, said at least another layer ofoxide is silicon dioxide having a silicon content therein in excess ofthat in said first layer. .Iaddend.